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4.2 Interrupt Configuration Registers (IRQCFG)
0x0D - IRQCFG0D [default 0x00]
Name
Bits
R/W
Description
IRQ0 source in receive mode:
Continuous data mode -
00 → IRQ0 mapped to pattern signal
01 → IRQ0 mapped to RSSI_IRQ
10,11 → IRQ0 mapped to start pattern detect
Buffered data mode -
00 → IRQ0 set to 0
RX_IRQ0
7,6
r/w
01 → IRQ0 mapped to Write_byte
10 → IRQ0 mapped to nFIFOEMPY (also in Standby mode)
11 → IRQ0 mapped to start pattern detect
Packet data mode -
00 → IRQ0 mapped to Data_Rdy signal
01 → IRQ0 mapped to Write_byte
10 → IRQ0 mapped to nFIFOEMPY (also in Standby mode)
11 → IRQ0 mapped to Node Address Match if ADDRS_cmp is enabled
11 → IRQ0 mapped to Start Pattern Detect if ADDRS_cmp is not enabled
IRQ1 source in receive mode.
Continuous data mode -
00 → IRQ1 mapped to DCLK signal
01,10,11 → IRQ1 mapped to DCLK
Buffered data mode -
00 → IRQ1 set to 0
RX_IRQ1
5,4
r/w
01 → IRQ1 mapped to FIFOFULL
10 → IRQ1 mapped to RSSI_IRQ
11 → IRQ1 mapped to FIFO_Int_Rx (also in Standby mode)
Packet data mode -
00 → IRQ1 mapped to CRC_OK
01 → IRQ1 mapped to FIFOFULL (also in Standby mode)
10 → IRQ1 mapped to RSSI_IRQ
11 → IRQ1 mapped to FIFO_Int_Rx (also in Standby mode)
IRQ0 source in transmit mode:
Continuous data mode -
TX_IRQ0
3
r/w
0,1 → IRQ0 set to 0
Buffered or Packet data modes -
0 → IRQ0 mapped to FIFO_thresh (transmission starts when IRQ0 switches high)
1 → IRQ0 is mapped to nFIFOEMPY (transmission starts when IRQ0 switches high)
IRQ1 source in transmit mode.
Continuous data mode -
TX_IRQ1
2
r
0, 1→ IRQ_1 mapped to DCLK
Buffered or Packet data modes -
0 → IRQ1 mapped to FIFOFULL
1 → I RQ1 is mapped to TX_Stop
FIFOFULL
nFIFOEMPY
1
0
r
r
FIFO full (IRQ source)
low when FIFO empty (IRQ source).
Table 28
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TRC105 - 05/29/13
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